Stop hoping for the best: Fully verify Serdes designs before manufacture
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Event hosted by Siemens Electronic Systems Design & Manufacturing
January 16, 2024 – January 16, 2024Online event
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“Right first time” is a goal we all aspire to, but how often does it really happen? Even when we follow layout rules as closely as possible, problems creep into the layout that cause issues during lab testing and result in costly, time-consuming respins.
Join our expert presenter Todd Westerhoff in this LinkedIn Live session where he will dive into why this happens and how to address it through a multifaceted approach that involves meticulous consideration of board fabrication nuances such as layer thickness and conductivity, and ensuring simulations actually model the board as implemented (instead of the board as intended) by using automated post-layout verification that extracts, models and analyzes all the design's serial channels instead of only a select few.